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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Camposano, R. |
| Copyright Year | 1996 |
| Description | Author affiliation: Synopsys Inc., Mountain View, CA, USA (Camposano, R.) |
| Abstract | Since the 1988 tutorial on behavioral (high-level) synthesis which appeared in the DAC proceedings (and later in the proceedings of the IEEE) much has happened in the field. Behavioral synthesis is now considered mainstream EDA as evidenced by the number of articles at conferences, journals and books. May be even more significant, several products are being offered commercially, and the number of designers using behavioral synthesis is probably in the hundreds. The initial promise of behavioral synthesis, to dramatically increase productivity by elevating the level of design, has been fulfilled. The increase in productivity of behavioral design versus RTL design is typically quoted at 5 times. What came as a surprise to most researchers in the field, is that this is achieved without impacting the quality of results (area, timing)! If anything, behavioral designs are slightly smaller and faster that their RTL counterparts, mainly because much more architectural exploration can be afforded at the behavioral level, thus providing a better starting point for synthesis. |
| Starting Page | 33 |
| Ending Page | 34 |
| File Size | 250133 |
| Page Count | 2 |
| File Format | |
| ISBN | 0780332946 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.1996.545540 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-06-03 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Registers Application software Permission Productivity Digital signal processing Electronic design automation and methodology Books Timing Logic Algorithm design and analysis |
| Content Type | Text |
| Resource Type | Article |
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