NDLI: Glitch analysis and reduction in register transfer level power optimization

Content Provider	IEEE Xplore Digital Library
Author	Raghunathan, A. Dey, S. Jha, N.K.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Raghunathan, A.)
Abstract	We present design-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the control and data path parts of the circuit. Based on the analysis, we develop techniques that attempt to reduce glitching power consumption by minimizing generation and propagation of glitches in the RTL circuit. Our techniques include restructuring multiplexer networks (to enhance data correlations, eliminate glitchy control signals, and reduce glitches on data signals), clocking control signals, and inserting selective rising/falling delays. Our techniques are suited to control-flow intensive designs,where glitches generated at control signals have a significant impact on the circuit's power consumption, and multiplexers and registers often account for a major portion of the total power. Application of the proposed techniques to several examples shows significant power savings, with negligible area and delay overheads.
Starting Page	331
Ending Page	336
File Size	765501
Page Count	6
File Format	PDF
ISBN	0780332946
ISSN	0738100X
DOI	10.1109/DAC.1996.545596
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Power generation Multiplexing Registers Permission National electric code Clocks Automatic generation control Circuit analysis Signal design
Content Type	Text
Resource Type	Article

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