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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hao Shen Petrot, F. |
| Copyright Year | 2010 |
| Description | Author affiliation: System Level Synthesis Group, TIMA Laboratory, CNRS/Grenoble INP/UJF, 43, Avenue Félix Viallet, 38031, France (Hao Shen; Petrot, F.) |
| Abstract | Multiple Configurable Processors System-on-Chip (MCPSoC) platforms have both performance and power advantages for embedded applications. Unfortunately, at early design stages, because of the processor configuration, I/O device changes and MCPSoC architecture modifications, designers waste much time on the Operating System (OS) porting work with general Instruction Set Simulator (ISS) based SoC simulation platforms. In this paper, we propose a hybrid simulation platform which uses general ISS and implements the Hardware Abstraction Layer (HAL) Application Programming Interfaces (APIs) and I/O device driver APIs with the SystemC modules on host machines directly. This hybrid simulation platform can shorten the application validation process by avoiding assembly code and hard-coded address modifications of traditional OS porting work. We show the advantages of our new hybrid simulation platform with a video decoding case study in the end. |
| Starting Page | 155 |
| Ending Page | 160 |
| File Size | 285473 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424457656 |
| DOI | 10.1109/ASPDAC.2010.5419904 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-01-18 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware System-on-a-chip Embedded system Operating systems Assembly systems Instruction sets Context modeling Switches Costs Application specific processors |
| Content Type | Text |
| Resource Type | Article |
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