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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tanaka, H. Ota, Y. Matsumoto, N. Hieda, T. Takeuchi, Y. Imai, M. |
| Copyright Year | 2010 |
| Description | Author affiliation: Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan (Tanaka, H.; Ota, Y.; Matsumoto, N.) || Graduate School of Information Science and Technology, Osaka University, 1-5 Yamadaoka, Suita, 565-0871, Japan (Hieda, T.; Takeuchi, Y.; Imai, M.) |
| Abstract | Although SIMD instructions are effective for many digital signal processing applications, current compilers cannot take full advantage of SIMD instructions. One factor inhibiting SIMD code generation is control flow structure; the target scope of SIMD code generation is currently limited to single basic block or loop that consists of single basic block. SIMD instructions cannot be mapped typically across basic block boundaries even if basic blocks inside the control structure have enough parallelism. In this paper, a new compilation technique to generate SIMD code without modifying control flow structure is proposed. The data dependency between basic blocks is exploited to generate SIMD instructions. The packing cost is introduced for effective vectorization to maintain data dependency across basic block boundaries. Experimental results show that the new SIMD code generation technique reduced 67% of dynamic execution cycles of inter prediction in H.264 decoder. |
| Starting Page | 101 |
| Ending Page | 106 |
| File Size | 1259850 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424457656 |
| DOI | 10.1109/ASPDAC.2010.5419911 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-01-18 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Microprocessors Automatic control Digital signal processing Costs Decoding Hardware Signal generators Research and development Information science Parallel processing |
| Content Type | Text |
| Resource Type | Article |
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