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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jin-Fu Li Cheng-Wen Wu |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Electrical Engineering, Tsing-Hua University, Hsinchu, Taiwan (Cheng-Wen Wu) || Department of Electrical Engineering, National Central University, Jhongli, Taiwan (Jin-Fu Li) |
| Abstract | Three-dimensional (3D) integration using through silicon via (TSV) is an emerging technology for integrated circuit designs. 3D integration technology provides numerous opportunities to designers looking for more cost-effective system chip solutions. In addition to stacking homogeneous memory dies, 3D integration technology supports heterogeneous integration of memories, logic, sensors, etc. It eases the interconnect performance limitation, provides higher functionality, results in small form factor, etc. On the other hand, there are challenges that should be overcome before volume production of TSV-based 3D ICs becomes possible, e.g., technological challenges, yield and test challenges, thermal and power challenges, infrastructure challenges, etc. |
| Starting Page | 541 |
| Ending Page | 543 |
| File Size | 155039 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424457656 |
| DOI | 10.1109/ASPDAC.2010.5419826 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-01-18 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit technology Silicon Through-silicon vias Integrated circuit synthesis Stacking Logic Integrated circuit interconnections Power system interconnection Production Testing |
| Content Type | Text |
| Resource Type | Article |
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