NDLI: Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

Content Provider	IEEE Xplore Digital Library
Author	Zhiyuan He Zebo Peng Eles, P. Rosinger, P. Al-Hashimi, B.M.
Copyright Year	2006
Description	Author affiliation: Embedded Syst. Lab., Linkoping Univ. (Zhiyuan He; Zebo Peng; Eles, P.)
Abstract	High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test time and, at the same time, prevent the temperature of cores under test going over the given upper limit. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling spans between test sequences, so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, in order to utilize the cooling spans and the test bus bandwidth for test data transportation, hence the total test time is reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use constraint logic programming to solve it in order to obtain the optimal solution. Experimental results have shown the efficiency of the proposed approach
Starting Page	477
Ending Page	485
File Size	230482
Page Count	9
File Format	PDF
ISBN	076952706X
ISSN	15505774
DOI	10.1109/DFT.2006.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interleaved codes Cooling System-on-a-chip System testing Temperature distribution Bandwidth Road transportation Logic testing Constraint optimization Logic programming
Content Type	Text
Resource Type	Article

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