NDLI: Message from the Symposium Chair

Please wait, while we are loading the content...

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Title

21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Copyright

Message from the Symposium Chair

Adaptive Design for Performance-Optimized Robustness

Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates

Gate Failures Effectively Shape Multiplexing

Test Generation for Open Defects in CMOS Circuits

Implicit Critical PDF Test Generation with Maximal Test Efficiency

Selecting High-Quality Delay Tests for Manufacturing Test and Debug

Testing Reversible 1D Arrays for Molecular QCA

Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design

Error Tolerance of DNA Self-Assembly by Monomer Concentration Control

Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects

A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices

Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor

A Novel Methodology for Functional Test Data Compression

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters

An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint

Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC

Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost

Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems

Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique

Low Power SoC Memory BIST

Synthesis of Efficient Linear Test Pattern Generators

An Approach to Minimizing Functional Constraints

Reliability Evaluation of Repairable/Reconfigurable FPGAs

Reliability Analysis of Self-Repairable MEMS Accelerometer

Timing Failure Analysis of Commercial CPUs Under Operating Stress

Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis

Combined software and hardware techniques for the design of reliable IP processors

Low-Cost Hardening of Image Processing Applications Against Soft Errors

Online hardening of programs against SEUs and SETs

Equivalent IDDQ Tests for Systems with Regulated Power Supply

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

Bilateral Testing of Nano-scale Fault-tolerant Circuits

A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects

SET Fault Tolerant Combinational Circuits Based on Majority Logic

An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm

A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy

Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers

Recovery Mechanisms for Dual Core Architectures

A Software-Based Error Detection Technique Using Encoded Signatures

Effective Post-BIST Fault Diagnosis for Multiple Faults

Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method

On-Line Mapping of In-Field Defects in Image Sensor Arrays

Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies

NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations

Multi-Site and Multi-Probe Substrate Testing on an ATE

Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream

The Filter Checker: An Active Verification Management Approach

Effect of Process Variation on the Performance of Phase Frequency Detector

Data Dependent Jitter Characterization Based on Fourier Analysis

A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells

A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network

VLSI Implementation of a Fault-Tolerant Distributed Clock Generation

Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in