NDLI: Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design

Content Provider	IEEE Xplore Digital Library
Author	Choi, Mi. Choi, My. Patitz, Z. Park, N.
Copyright Year	2006
Description	Author affiliation: Dept. of ECE, Missouri-Rolla Univ., Rolla, MO (Choi, Mi.)
Abstract	The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges. The most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This issue is commonly referred to as the "layout =timing" problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the locally synchronous, globally asynchronous design for QCA has been recently proposed. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design is be possible. Also, the proposed technique is more scalable in designing large-scale systems. Since a less number of cells is used, the overall area is smaller and the manufacturability is better. In this paper, numerous multi-bit adder designs are considered to demonstrate the layout efficiency and robustness of the proposed globally asynchronous QCA design technique
Starting Page	80
Ending Page	88
File Size	712206
Page Count	9
File Format	PDF
ISBN	076952706X
ISSN	15505774
DOI	10.1109/DFT.2006.25
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Quantum cellular automata Robustness Delay Quantum dots Clocks Circuit synthesis Synchronization Very large scale integration Timing Flexible printed circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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