NDLI: Application of CGS stress metrology to advanced process control & monitoring

Content Provider	IEEE Xplore Digital Library
Author	Owen, D.M. Hebb, J. Otten, C.
Copyright Year	2011
Description	Author affiliation: Ultratech, Inc. San Jose, CA 95134, USA (Owen, D.M.; Hebb, J.) \|\| Texas Instruments Inc. Dallas, TX 75243 (Otten, C.)
Abstract	The improvement of device performance associated with the intentional manipulation of stresses on the transistor scale is an integral part of device fabrication at advanced technology nodes. However, comparatively little attention is given to stress management at within-die and within-wafer length scales. Process variations that occur on these longer length scales can induce significant within-wafer stress variations. In turn, the die-to-die, wafer-to-wafer and lot-to-lot stress variations may have significant impact on device performance and yield. This paper describes the use of the CGS (Coherent Gradient Sensing) stress metrology to characterize the detailed within-wafer and wafer-to-wafer stress variations. The CGS stress maps consist of more than 700,000 data points, enabling new potential applications for stress metrology. Case studies are presented that summarize the use of the CGS data to reveal correlations between stress variations and device performance, lithographic overlay and tool matching.
Starting Page	1
Ending Page	6
File Size	548495
Page Count	6
File Format	PDF
ISBN	9781612844084
ISSN	10788743
e-ISBN	9781612844091
DOI	10.1109/ASMC.2011.5898171
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Performance evaluation Substrates Correlation MOS devices Stress measurement Annealing device yield stress metrology process control
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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