NDLI: The effect of hafnium or zirconium contamination on MOS processes

Content Provider	IEEE Xplore Digital Library
Author	Vermeire, B. Delbridge, K. Pandit, V. Parks, H.G. Raghavan, S. Ramkumar, K. Geha, S. Jeon, J.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA (Vermeire, B.; Delbridge, K.; Pandit, V.; Parks, H.G.)
Abstract	Hf and Zr contamination during immersion in process solutions is most likely to occur in neutral or caustic solutions. Both Hf and Zr contamination are introduced onto the wafer surface if they are present in an APM solution (which is caustic), but such contamination is easily removed using existing cleans. If contamination remains on a wafer, an effect on gate oxide integrity using ramped voltage testing is only observed at very high concentrations of Hf. Time dependent dielectric breakdown results are affected at lower levels of contamination. This is true particularly if the contamination is introduced using an APM solution. Wafer-to-wafer cross contamination can also occur in a thermal reactor during high temperature anneals of high-k dielectric layers.
Sponsorship	IEEE Electron Devices Soc. Components, Packagin & Manuf. Technol. Soc. MICRO
Starting Page	299
Ending Page	303
File Size	444697
Page Count	5
File Format	PDF
ISBN	0780371585
DOI	10.1109/ASMC.2002.1001622
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hafnium Zirconium Surface contamination Breakdown voltage Testing Dielectric breakdown Inductors Temperature Annealing High-K gate dielectrics
Content Type	Text
Resource Type	Article

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