NDLI: Wafer back side inspection applications for yield protection and enhancement

Content Provider	IEEE Xplore Digital Library
Author	Cheema, L.A. Olmer, L.J. Patterson, O.D. Lopez, S.S. Burns, M.B.
Copyright Year	2002
Description	Author affiliation: Agere Syst., Orlando, FL, USA (Cheema, L.A.; Olmer, L.J.; Patterson, O.D.)
Abstract	Semiconductor manufacturers employ various techniques and tools to detect and identify the physical defects that limit product and process yields. Most of these techniques focus on measuring the front side of the semiconductor wafer where the devices are manufactured. Attention to defectivity on the wafer backside has been minimal. Two possible reasons are the lack of suitable equipment and methods, and a lack of awareness of how backside defectivity can affect a manufacturing line. This paper presents four case studies which describe how back side defectivity can affect yield, scrap and production costs. New technology, which facilitates backside inspection, has recently been developed. Key improvements include the ability to non-destructively scan wafer backsides and improved coordinate accuracy, which allows adder calculations and SEM review. This paper describes how this new technology was applied in these case studies, thereby improving yield and reducing scrap and production costs.
Sponsorship	IEEE Electron Devices Soc. Components, Packagin & Manuf. Technol. Soc. MICRO
Starting Page	64
Ending Page	71
File Size	1110928
Page Count	8
File Format	PDF
ISBN	0780371585
DOI	10.1109/ASMC.2002.1001576
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protection Semiconductor device manufacture Costs Manufacturing processes Production Semiconductor lasers Monitoring Electronics industry Automatic optical inspection CMOS technology
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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