NDLI: Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications

Content Provider	IEEE Xplore Digital Library
Author	Ghasemi, H.R. Karpuzcu, U.R. Nam Sung Kim
Copyright Year	2015
Description	Author affiliation: ECE Dept., Univ. of Minnesota, Minneapolis, MN, USA (Karpuzcu, U.R.) \|\| ECE Dept., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Nam Sung Kim) \|\| CS Dept., Univ. of Wisconsin-Madison, Madison, WI, USA (Ghasemi, H.R.)
Abstract	Mobile computing devices demand processors to offer a wide range of performance/power trade-offs so that they can provide much needed high performance or low power consumption depending on a given operating requirement. While dynamic voltage/frequency scaling (DVFS) has been the most powerful technique to provide such trade-offs, few processor vendors have the capability to provide a sufficient DVFS range requiring joint optimization of devices and circuits. Facing such a challenge, two promising approaches are proposed: scaling the amount of processor resources such as on-chip memory and execution units, i.e., dynamic resource scaling (DRS) and switching between big out-of-order (OoO) and little in-order cores in a single-ISA heterogeneous processor such as ARM's big. LITTLE. In this paper, we compare a single-ISA heterogeneous processor with a wide dynamic range (WDR) processor augmented with DRS in terms of (1) device-, circuit-, architecture-level implications, (2) design challenges, (3) area, (4) performance, and (5) energy efficiency. We evaluate a big. LITTLE processor (as a representative of single-ISA heterogeneous processor) based on Cortex-A15/A7 and a WDR processor based on Cortex-A15 running various mobile and SPEC2006 benchmarks. Our experiments demonstrate that the WDR processor combined with DRS can deliver energy efficiency close to the single-ISA heterogeneous processor, depending on the power overhead of circuit implementation to provide the wide DVFS range.
Sponsorship	IEEE
Starting Page	304
Ending Page	310
File Size	216485
Page Count	7
File Format	PDF
e-ISBN	9781467371667
DOI	10.1109/ICCD.2015.7357118
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Computer architecture Energy efficiency Dynamic range Performance evaluation Optimization Dynamic scheduling
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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