NDLI: InvArch: A hardware eficient architecture for Matrix Inversion

Content Provider	IEEE Xplore Digital Library
Author	Cheema, U.I. Nash, G. Ansari, R. Khokhar, A.A.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA (Khokhar, A.A.) \|\| Dept. of Electr. & Comput. Eng., Univ. of Illinois at Chicago, Chicago, IL, USA (Cheema, U.I.; Nash, G.; Ansari, R.)
Abstract	This paper proposes an efficient architecture (InvArch) for computing matrix inversion using Gauss-Jordan Elimination method. The proposed architecture exploits parallelism through pipelined floating-point computational units and reduces the number of floating-point multiplication units required compared with the existing pipelined implementations. The reduction in multiplication units results in over 80% reduction in hardware for floating point computation units. The architecture performs in-place inversion and provides scalability across the rows and columns. Hardware efficiency is achieved by reaping benefit from regularity in computation and better utilization of pipelined computational resources. Multiple rows are normalized within an iteration of Gauss-Jordan algorithm that allows reduction in number of floating-point multiplication units in the elimination step. In addition to implementing the architecture, an analytical performance model is also developed for InvArch and some related works. InvArch achieves performance comparable to reference architectures in terms of clock cycles and throughput while using significantly less hardware resources.
Sponsorship	IEEE
Starting Page	180
Ending Page	187
File Size	1528312
Page Count	8
File Format	PDF
e-ISBN	9781467371667
DOI	10.1109/ICCD.2015.7357100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Hardware Pipelines Random access memory Field programmable gate arrays Computers Scalability
Content Type	Text
Resource Type	Article

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