NDLI: Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems

Content Provider	IEEE Xplore Digital Library
Author	Silva, B. Delbem, A. Bonato, V. Diniz, P.C.
Copyright Year	2015
Description	Author affiliation: Inst. de Cienc. Mat. e de Comput., Univ. de Sao Paulo, Sao Carlos, Brazil (Silva, B.; Delbem, A.; Bonato, V.) \|\| USC Inf. Sci. Inst., Marina del Rey, CA, USA (Diniz, P.C.)
Abstract	Heterogeneous Multi-core Processors (HMPs) have the potential to outperform homogeneous multi-core processors in terms of raw performance and/or energy as both their Instruction-Set Architectures (ISA) and cache configurations (size and set associativity) can be tailored to the specific needs of a computation. In this paper we describe algorithm for the generation of custom HMP and a dynamic run-time core-mapping and scheduling policy that exploits the heterogeneity of such systems customized with respect to the number of cores and L1 cache memory sizes. Experimental results targeting custom HMPs implemented on a contemporary Field-Programmable Gate Array (FPGA) with LEON3 cores as their base for a set of 50 application codes reveal that the proposed core-mapping and scheduling algorithms achieves an average execution time improvement of 18.3% and a 12% energy reduction over a static core-mapping and list-scheduling algorithms.
Starting Page	1
Ending Page	6
File Size	1559439
Page Count	6
File Format	PDF
e-ISBN	9781467394062
DOI	10.1109/ReConFig.2015.7393355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-07
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	mapping and scheduling policies Energy consumption Multicore processing Heuristic algorithms power/performance optimization Dynamic scheduling Hardware heterogeneous multi-core processors Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in