NDLI: Sequential hardware Trojan: Side-channel aware design and placement

Content Provider	IEEE Xplore Digital Library
Author	Xinmu Wang Narasimhan, S. Krishna, A. Mal-Sarkar, T. Bhunia, S.
Copyright Year	2011
Description	Author affiliation: Electrical Engineering and Computer Science Department, Case Western Reserve University, USA (Xinmu Wang; Narasimhan, S.; Krishna, A.; Bhunia, S.) \|\| Hathaway Brown High School, Cleveland, OH, USA (Mal-Sarkar, T.)
Abstract	Various design-for-security (DFS) approaches have been proposed earlier for detection of hardware Trojans, which are malicious insertions in Integrated Circuits (ICs). In this paper, we highlight our major findings in terms of innovative Trojan design that can easily evade existing Trojan detection approaches based on functional testing or side-channel analysis. In particular, we illustrate design and placement of sequential hardware Trojans, which are rarely activated/observed and incur ultralow delay/power overhead. We provide models, examples, theoretical analysis of effectiveness, and simulation as well as measurement results of impact of these Trojans in a hardened design. It is shown that efficient design and placement of sequential Trojan would incur extremely low side-channel (power, delay) signature and hence, can easily evade both post-silicon validation and DFS (e.g. ring oscillator based) approaches.
Starting Page	297
Ending Page	300
File Size	1352654
Page Count	4
File Format	PDF
ISBN	9781457719530
ISSN	10636404
e-ISBN	9781457719547
DOI	10.1109/ICCD.2011.6081413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Trojan horses Radiation detectors Logic gates Delay Hardware Payloads Field programmable gate arrays DFS Hardware Trojan Attacks Sequential Trojan
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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