NDLI: Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Moradi, F. Panagopoulos, G. Karakonstantis, G. Wisland, D. Mahmoodi, H. Madsen, J.K. Roy, K.
Copyright Year	2011
Description	Author affiliation: Swiss Federal Institute of Technology (EPFL), Switzerland (Karakonstantis, G.) \|\| Nanoelectronics Group, University of Oslo, Norway (Moradi, F.; Wisland, D.) \|\| Nanoelectronic Research Lab, Purdue University, USA (Panagopoulos, G.; Roy, K.) \|\| Aarhus School of Engineering, Aarhus University, Denmark (Madsen, J.K.) \|\| NeCRL Group, San Francisco State University, USA (Mahmoodi, H.)
Abstract	In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.
Starting Page	326
Ending Page	331
File Size	4386675
Page Count	6
File Format	PDF
ISBN	9781457719530
ISSN	10636404
e-ISBN	9781457719547
DOI	10.1109/ICCD.2011.6081419
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Transistors Capacitance Delay Noise Boosting Arrays
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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