NDLI: Enhancing topological ATPG with high-level information and symbolic techniques

Content Provider	IEEE Xplore Digital Library
Author	Corno, F. Patel, J.K. Rudnick, E.M. Sonza Reorda, M. Vietti, R.
Copyright Year	1998
Description	Author affiliation: Dipt. di Autom. e Inf., Politecnico di Torino, Italy (Corno, F.)
Abstract	This paper proposes a method to enhance topological ATPG algorithms by exploiting some information computed through symbolic techniques. Since symbolic techniques can only be applied to small circuits, suitable circuit portions (named macros) are first selected, and then symbolic techniques are used to analyze their state graphs. The topological ATPG algorithm benefits from this analysis to bound its search tree. Experimental results show that the proposed approach is effective in reducing the required CPU time and increasing both the Fault Coverage and the Fault Efficiency. When high-level information about the circuit behavior and structure is available, it can be fruitfully exploited for macro selection.
Starting Page	504
Ending Page	509
File Size	50743
Page Count	6
File Format	PDF
ISBN	0818690992
ISSN	10636404
DOI	10.1109/ICCD.1998.727096
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit testing Circuit faults State-space methods Partitioning algorithms Central Processing Unit Binary decision diagrams High performance computing Read only memory Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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