NDLI: Improved built-in test pattern generators based on comparison units for synchronous sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Pomeranz, I. Reddy, S.M.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Pomeranz, I.)
Abstract	We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determination of the test sequence applied to the circuit-under-test, using fewer logic gates than the original scheme. In addition, a procedure to match the parameters of the test pattern generator to the circuit-under-test is proposed to replace the random selection used in the basic scheme. The effectiveness of these improvements is demonstrated through experimental results.
Starting Page	26
Ending Page	31
File Size	46094
Page Count	6
File Format	PDF
ISBN	0818690992
ISSN	10636404
DOI	10.1109/ICCD.1998.727019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Test pattern generators Circuit testing Logic testing Synchronous generators Sequential circuits Flexible printed circuits Logic gates Logic circuits Pattern matching
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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