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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wadekar, S.A. Parker, A.C. |
| Copyright Year | 1998 |
| Description | Author affiliation: Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA (Wadekar, S.A.) |
| Abstract | In typical hardware implementations of an arithmetic-intensive algorithm, designers must determine the word lengths of resources such as adders, multipliers, and registers. This paper presents algorithmic level theory and optimization techniques to select distinct word lengths for each computation which meet the desired accuracy and minimize the design cost for the given performance constraints. The reduction in cost is possible by avoiding unnecessary bit-level computations that do not contribute significantly to the accuracy of the final results. Thus we have introduced a new optimization variable, computation accuracy, into data-path synthesis. Our results show on an average, a 30% reduction in functional-resource area using distinct word lengths as opposed to use of a single optimized word length for the entire algorithm. |
| Starting Page | 54 |
| Ending Page | 61 |
| File Size | 128434 |
| Page Count | 8 |
| File Format | |
| ISBN | 0818690992 |
| ISSN | 10636404 |
| DOI | 10.1109/ICCD.1998.727023 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-10-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Cost function Arithmetic Manuals Government Algorithm design and analysis Clustering algorithms Computer architecture Multiplexing Registers Design optimization |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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