NDLI: Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Content Provider	IEEE Xplore Digital Library
Author	Oliver, J. Rao, R. Sultana, P. Crandall, J. Czernikowski, E. Jones IV, L.W. Franklin, D. Akella, V. Chong, F.T.
Copyright Year	2004
Description	Author affiliation: California Univ., Davis, CA, USA (Oliver, J.; Rao, R.; Sultana, P.; Crandall, J.; Czernikowski, E.)
Abstract	We present Synchroscalar, a tile-based architecture for embedded processing that is designed to provide the flexibility of DSPs while approaching the power efficiency of ASICs. We achieve this goal by providing high parallelism and voltage scaling while minimizing control and communication costs. Specifically, Synchroscalar uses columns of processor tiles organized into statically-assigned frequency-voltage domains to minimize power consumption. Furthermore, while columns use SIMD control to minimize overhead, data-dependent computations can be supported by extremely flexible statically-scheduled communication between columns. We provide a detailed evaluation of Synchroscalar including SPICE simulation, wire and device models, synthesis of key components, cycle-level simulation, and compiler- and hand-optimized signal processing applications. We find that the goal of meeting, not exceeding, performance targets with data-parallel applications leads to designs that depart significantly from our intuitions derived from general-purpose microprocessor design. In particular, synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect supports parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Overall, Synchroscalar provides programmability while achieving power efficiencies within 8-30/spl times/ of known ASIC implementations, which is 10-60/spl times/ better than conventional DSPs. In addition, frequency-voltage scaling in Synchroscalar provides between 3-32% power savings in our application suite.
Sponsorship	ACM SIGARCH IEEE Comput. Soc. TCCA
Starting Page	150
Ending Page	161
File Size	438784
Page Count	12
File Format	PDF
ISBN	0769521436
ISSN	10636897
DOI	10.1109/ISCA.2004.1310771
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-23
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Digital signal processing Communication system control Computational modeling Signal processing Process design Parallel processing Voltage control Costs Tiles
Content Type	Text
Resource Type	Article

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Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor (2004)

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor.

Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor (2004)

Synchroscalar:A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Using application bisection bandwidth to guide tile size selection for the synchroscalar tile-based architecture.

Compilation for interprocessor communication in clock-skewed parallel processing system

Low power network processor design using clock gating

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

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