NDLI: Field-testing IMPACT EPIC research results in Itanium 2

Content Provider	IEEE Xplore Digital Library
Author	Sias, J.W. Sain-zee Ueng Kent, G.A. Steiner, I.M. Nystrom, E.M. Hwu, W.-M.W.
Copyright Year	2004
Description	Author affiliation: Dept. of Reliable & High-Performance Comput., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Sias, J.W.; Sain-zee Ueng; Kent, G.A.; Steiner, I.M.; Nystrom, E.M.; Hwu, W.-M.W.)
Abstract	Explicitly-Parallel Instruction Computing (EPIC) provides architectural features, including predication and explicit control speculation, intended to enhance the compiler's ability to expose instruction-level parallelism (ILP) in control-intensive programs. Aggressive structural transformations using these features, though described in the literature, have not yet been fully characterized in complete systems. Using the Intel Itanium 2 microprocessor, the SPECint2000 benchmarks and the IMPACT Compiler for IA-64, a research compiler competitive with the best commercial compilers on the platform, we provide an in situ evaluation of code generated using aggressive, EPIC-enabled techniques in a reality-constrained microarchitecture. Our work shows a 1.13 average speedup (up to 1.50) due to these compilation techniques, relative to traditionally-optimized code at the same inlining and pointer analysis levels, and a 1.55 speedup (up to 2.30) relative to GNU GCC, a solid traditional compiler. Detailed results show that the structural compilation approach provides benefits far beyond a decrease in branch misprediction penalties and that it both positively and negatively impacts instruction cache performance. We also demonstrate the increasing significance of runtime effects, such as data cache and TLB, in determining end performance and the interaction of these effects with control speculation.
Sponsorship	ACM SIGARCH IEEE Comput. Soc. TCCA
Starting Page	26
Ending Page	37
File Size	426538
Page Count	12
File Format	PDF
ISBN	0769521436
ISSN	10636897
DOI	10.1109/ISCA.2004.1310761
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-23
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Microarchitecture Computer aided instruction Concurrent computing Program processors Clocks Pipelines Microprocessors Solids Runtime
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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