Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

Article

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor (2004)

Thesis

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Article

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor.

Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor (2004)

Proceeding

Integrated cpu cache power management in multiple clock domain processors.

Article

The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems

Article

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Article

An FPGA-based scalable simulation accelerator for tile architectures

Article