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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hassan, R.O. Abdelhalim, M.B. Habib, S.E.-D. |
| Copyright Year | 2013 |
| Description | Author affiliation: Electron. & Commun. Eng. Dept., Cairo Univ., Cairo, Egypt (Hassan, R.O.; Habib, S.E.-D.) || CCIT-AASTMT, Cairo, Egypt (Abdelhalim, M.B.) |
| Abstract | Hardware and Software co-design has become one of the main methodologies in modern embedded systems. The partitioning step, i.e. to decide which components of the system should be implemented in hardware and which ones in software, is the most important step in the embedded systems. Since the costs and delays of the final design strongly depend on partitioning results, there is a need to get an accurate estimate for hardware area, delay and power. However, accurate delay estimation methods are slow as they need a scheduling step. In this paper, we propose a reliable delay estimation method to be used within the partitioning step prior to the scheduling step. |
| Starting Page | 1246 |
| Ending Page | 1250 |
| File Size | 826279 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479900664 |
| ISSN | 15483746 |
| DOI | 10.1109/MWSCAS.2013.6674880 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-08-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | MPSOC Hardware/Software Co-design Hardware/Software Partitioning Control-Data Flow Graphs FPGAs High-level synthesis Design Space Exploration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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