NDLI: Fast FPGA-Based Delay Estimation for a Novel Hardware/Software Partitioning Scheme

Content Provider	IEEE Xplore Digital Library
Author	Abdelhalim, M.B. Habib, S.E.-D.
Copyright Year	2007
Description	Author affiliation: Cairo Univ., Giza (Abdelhalim, M.B.; Habib, S.E.-D.)
Abstract	In this paper a fast and accurate delay estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware as a single implementation, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound the area and latency ranges for different hardware implementations. The presented tool estimates the delay for these two hardware alternatives. Our delay modeling technique accounts for both the logic and routing delays so as to minimize the estimation error. The computational cost of the presented estimation tool depends linearly on the design complexity, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate with an average error of 4.2%.
Starting Page	175
Ending Page	181
File Size	1698268
Page Count	7
File Format	PDF
ISBN	9781424418244
DOI	10.1109/IDT.2007.4437454
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-16
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Delay estimation Hardware/Software Co-design Routing Delay Estimation Equations Embedded systems Hardware/Software Partitioning Embedded system Hardware Space exploration Field programmable gate arrays Clocks Testing
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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