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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chan-Bok Jeong Young-Ha Lee Hyeon-Deok Bae |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electron. Eng., Chungbuk Nat. Univ., Cheongju, South Korea (Hyeon-Deok Bae) || B4G Mobile Commun. Res. Dept., Electron. & Telecommun. Res. Inst., Daejeon, South Korea (Chan-Bok Jeong; Young-Ha Lee) |
| Abstract | This paper introduces a new framework to construct fast and efficient pseudo-random (PN) sequence generation for bit scrambling, called a J-delayed and K-dimensional Linear Feedback Shift Register (JKLFSR). In the proposed framework, we generate the state of a J-shifted LFSR using one clock and K-bit multiple outputs of a LFSR each clock cycle for scrambling/descrambling of large coded bits using an output of LFSR. JKLFSR is highly relevant for the scrambling/descrambling process for a high-speed mass data transmission in an LTE-Advanced system, as it has fast computation and supports clock-based processing. In addition, we show that JKLFSR has an efficient performance theoretically in generating PN sequences. H/W simulation results verify the validity of the theory and demonstrate that we reduced the processing time used for generating PN sequences from (J + DL) clocks to (1 + DL/K) clocks as compared with a conventional LFSR, where DL denotes the length of a data stream. |
| Starting Page | 433 |
| Ending Page | 436 |
| File Size | 953410 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479900664 |
| ISSN | 15483746 |
| DOI | 10.1109/MWSCAS.2013.6674678 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-08-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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