NDLI: Automated formal synthesis of Wallace Tree multipliers

Content Provider	IEEE Xplore Digital Library
Author	Hasan, O. Kort, S.
Copyright Year	2007
Description	Author affiliation: Concordia Univ., Montreal (Hasan, O.; Kort, S.)
Abstract	In this paper, we present a formal synthesis methodology that is capable of performing correct synthesis at almost all levels of abstraction and can be adapted to be used for most of the combinational digital circuits irrespective of their size and complexity. The proposed methodology calls for proving the correctness-preserving characteristic for the transformations that are required in the synthesis of a particular digital circuit in a higher-order-logic theorem prover. These correctness- preserving transformation proofs can then be used to automatically verify the correctness of the corresponding synthesis process within the theorem prover in an automated way. For illustration purposes, we present the construction of an automated formal synthesis tool for Wallace Tree multipliers based on our methodology.
Starting Page	293
Ending Page	296
File Size	270176
Page Count	4
File Format	PDF
ISBN	9781424411757
ISSN	15483746
DOI	10.1109/MWSCAS.2007.4488591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-05
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Digital circuits Bridge circuits Hardware design languages Embedded software Software performance Software tools Software algorithms Character generation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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