NDLI: A 100MS/s recycling 2-step ADC embedding programmable gain amplification for DVB satellite

Content Provider	IEEE Xplore Digital Library
Author	He-Gong Wei Chon-Kit Lai Seng-Pan, U. Martins, R.P.
Copyright Year	2007
Description	Author affiliation: Univ. of Macau, Macau (He-Gong Wei)
Abstract	A 100 MS/s, 6-bit recycling two-step analog-to- digital converter (ADC) with an embedded programmable gain amplification function is designed in 0.18-mum CMOS, being suitable for use in digital video broadcasting - satellites (DVB-S). In the proposed ADC, a programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) as well as a multiplying digital-to-analog converter (MDAC) are combined and merged into a single switched-capacitor (SC) block, thus providing good savings in terms of power and silicon area implementation. The proposed embedded PGA function optimizes efficiency in A/D conversion according to the dynamic input signal requirement of the DVB-S application. Full transistor-level simulation is provided for the ADC with 35-dB SNDR and 41-dB SFDR at 100 MS/s, and the DNL and INL are within plusmn0.6 and plusmn0.5 LSB, respectively. The proposed ADC consumes only 12 mW from a 1.8-V power supply.
Starting Page	132
Ending Page	135
File Size	789687
Page Count	4
File Format	PDF
ISBN	9781424411757
ISSN	15483746
DOI	10.1109/MWSCAS.2007.4488554
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-05
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Recycling Digital video broadcasting Electronics packaging Power amplifiers Circuits Satellite broadcasting Analog-digital conversion Capacitance Programmable logic arrays Very large scale integration
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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