NDLI: A comprehensive calibration scheme for a 14-b 50 MSPS pipeline ADC for multi-mode wireless receivers

Content Provider	IEEE Xplore Digital Library
Author	Jalali, B. Meruva, A.
Copyright Year	2007
Description	Author affiliation: Arizona State Univ., Tempe (Jalali, B.; Meruva, A.)
Abstract	Nonidealities of the analog circuitry that degrade the performance of pipeline analog to digital converters stem from different sources. Linear, nonlinear and memory errors in switched capacitor amplifier, nonlinearities in internal DAC, and errors in internal ADC all limit the achievable accuracy in a pipeline ADC. Although many calibration techniques have been proposed recently that tackle one or two of these errors, the need for a calibration engine that addresses them all is still remained. Such a comprehensive calibration engine is the key factor to achieve high resolution high speed pipeline converter. This paper proposes a new approach to compensate for higher order nonlinearities and combines that with existing techniques to correct for other types of errors (i.e. linear gain error, memory effect and DAC noise). A 14-bit 50 Msps pipeline ADC equipped with this comprehensive calibration engine is presented.
Starting Page	140
Ending Page	143
File Size	234519
Page Count	4
File Format	PDF
ISBN	9781424411757
ISSN	15483746
DOI	10.1109/MWSCAS.2007.4488556
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-05
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Pipelines Engines Error correction Circuits Capacitors Redundancy Signal processing Data mining Noise cancellation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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