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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Matthews, T.W. Heedley, P.L. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electr. & Electron. Eng., California State Univ., Sacramento, CA, USA (Matthews, T.W.; Heedley, P.L.) |
| Abstract | A simulation method that has proven valuable in the design of high-speed regenerative comparators such as those used in pipeline and flash analog-to-digital converters is presented. This method yields an input-referred offset voltage for the comparator while it is operating at speed, including both DC and dynamic effects such as charge injection and capacitive coupling. The speed and efficiency of the method allows the circuit designer to more fully explore the design space, and provides important insights into comparator operation. |
| Starting Page | 1815 |
| Ending Page | 1818 |
| File Size | 377350 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780391977 |
| DOI | 10.1109/MWSCAS.2005.1594475 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-08-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Testing Latches Threshold voltage Analog-digital conversion Space exploration Laboratories Regeneration engineering Design engineering Pipelines |
| Content Type | Text |
| Resource Type | Article |
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