NDLI: Integrating and verifying intellectual property blocks using platform express and ModelSim

Content Provider	IEEE Xplore Digital Library
Author	Wala, M. Bouldin, D.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN (Wala, M.; Bouldin, D.)
Abstract	Platform-based design is a proven method for minimizing the time and risks involved in designing and verifying a system-on-chip (SoC). Our experiences in using Mentor Graphics' platform express (PX) tool to design an SoC platform will be described in this paper. The tool allows intellectual property (IP) developers to add their IP cores and enables system designers to explore different system architectures rapidly by integrating pre-installed IP components. Thus, the designers work directly at the component level instead of the usual register-transfer description level. We have successfully added an open IP core to the PX component library and have used it in our system design. Also, since we intend to add only freely-available IP cores - or the ones that are internally generated - to expand our component library, it can be shared with anyone using platform express. This paper discusses integrating IP components to build a baseline platform for future, derivative SoC designs as well as verification for correctness using ModelSim. The complete IP integration and system design flow is outlined along with a workaround for designs involving IPs specified using both VHDL and Verilog. Pointers are also provided as recommendations for first-time users to avoid possible errors
Starting Page	758
Ending Page	761
File Size	355030
Page Count	4
File Format	PDF
ISBN	0780391977
DOI	10.1109/MWSCAS.2005.1594211
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Intellectual property Design engineering System-on-a-chip Computer graphics Libraries Electronic design automation and methodology Hardware design languages Digital signal processing chips Chip scale packaging Productivity
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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