NDLI: Low phase noise wideband VCO using MEMS

Content Provider	IEEE Xplore Digital Library
Author	Darade, B.S.
Copyright Year	2005
Description	Author affiliation: Jawaharlal Nehru Eng. Coll., Aurangabad, India (Darade, B.S.)
Abstract	Here I have attempted to design a low phase noise fully integrated VCO in 0.5/spl mu/m BiCMOS process with 10-20% tuning range. The VCO uses MOS capacitors for tuning and on-chip inductor as LC tank circuit. On-chip BiCMOS band gap bias network is implemented using MOSFETs operating in subthreshold region along with fast BJTs. It is giving precise response over desired range. Now primary aim is to maximize Q of the LC tank circuit to reduce phase noise. Now my attention is on incorporating on chip MEMS components for improving gain, power dissipation, phase noise, tuning performance of the VCO. For that two approaches are being in progress. First is to replace MOS capacitors by MEM tunable capacitors (using MEMS pro) technique of using reconfigurable comb drive mechanism is being incorporated. Its good for obtaining wide tuning but considering need for compact from factor presently MOS capacitor results dominates. Second is to design on-chip MEMS inductor. Also as designed inductor shows high loss translating into poor noise characteristic or low Q factors and becoming a major design bottleneck, moving toward MEMS inductor. I hope to optimize the tuning the tuning performance by tunable inductor.
Starting Page	155
Ending Page	158
File Size	342964
Page Count	4
File Format	PDF
ISBN	0780391977
DOI	10.1109/MWSCAS.2005.1594062
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Wideband Voltage-controlled oscillators Micromechanical devices Inductors MOS capacitors Circuit optimization BiCMOS integrated circuits Tunable circuits and devices Network-on-a-chip
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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