NDLI: Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme

Content Provider	IEEE Xplore Digital Library
Author	Santos, C. Ferrao, D. Lazzari, C. Wilke, G. Guntzel, J.L. Reis, R.
Copyright Year	2005
Description	Author affiliation: Inst. de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre (Santos, C.; Ferrao, D.; Lazzari, C.; Wilke, G.)
Abstract	This paper demonstrates the advantages in using a pin-to-pin delay model during the optimization of circuit performance. It is well known that pin-to-pin delay models are more accurate than a single pair of delays for gate level delay estimation, especially when complex gates are considered. For the transistor sizing problem, a pin-to-pin delay model can be used to size only the series-connected transistors passing by the gate input that belongs to the critical path. Experimental results show that performance is optimized with smaller transistor area overhead when only the critical transistors are sized instead of the whole pull-down or pull-up structure. Selective sizing approach achieved an average area gain of 1.5 for circuits containing only simple gates. For complex gate circuits the area gain ranges from 1.5 to 8.8. A fully automated library-free layout generator was used to evaluate the impact of the sizing approaches at layout level
Starting Page	315
Ending Page	318
File Size	168843
Page Count	4
File Format	PDF
ISBN	0780391977
DOI	10.1109/MWSCAS.2005.1594102
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay effects Delay estimation Electronic mail Timing Libraries Semiconductor device modeling Circuit optimization Design optimization Optimization methods Circuit synthesis
Content Type	Text
Resource Type	Article

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