NDLI: Counter mode encryption for FNBDT/MELP

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2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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2008 51st Midwest Symposium on Circuits and Systems

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Volume 3 - 2002

Power consumption behaviour of multiplier block algorithms

Using variable length 13-ary, radix-4 CSD coefficients to achieve low-area implementations of FIR filters

Design of linear-phase FIR filters combining subexpression sharing with MILP

The application of 2-D logarithms to low-power hearing-aid processors

Active noise control with weak nonlinearities in the secondary path

A novel algorithm for 2-D DOA estimation in the presence of impulsive noise

A new approach to soft parallel interference cancellation for synchronous CDMA

Rank-1 ambiguity DOA estimation of circular array with fewer sensors

A neuro-controller with guaranteed stability

Smoothing the control action for NARMA-L2 controllers

The OSU Multi-Vehicle Coordination Testbed

Autonomous robot navigation system using a novel value encoded genetic algorithm

The output distribution of fuzzy weighted median filters

On the Teager-Kaiser energy operator "low frequency error"

A new technique for motion estimation of microorganisms in the Hartley domain

A 2-D filtering structure with neural networks for Gaussian noise cancellation and edge preservation in images

Improving analysis techniques for automatic speech recognition

Language identification using shifted delta cepstra

Internet-accessible speech recognition technology

Sensitivity of MIL-STD-3005 MELP to packet loss on IP networks

Analysis of nonpreemptive priority queueing of MPLS networks with bulk arrivals

A novel analysis of queue length in differentiated services networks with self-similar arrival processes

Mobility: a VPN perspective [mobile computing]

MPLS multicasting through enhanced LDP and RSVP-TE control

Multilayer recurrent neural networks [character recognition application example]

Adaptive neural network filtering device for enhanced downhole oilfield measurements

Robust synthesis in /sub 1/ via /spl mu/ approach and D-K iteration [Space Shuttle example]

Control of chaotic heart conditions using synchronization

Optimal synthesis of state-estimate feedback analog controllers with minimum L/sub 2/-sensitivity

Representation of antenna calibration data using modular neural networks

A new neuro-based state estimator

Output tracking control of nonminimum phase systems via causal inversion

Spiking networks for biochemical detection

Multiple model based flight control design

A 100MHz 7/sup th/-order g/sub m/-C filter with a wide-range transconductance amplifier

A 2.5-V, 0.35 /spl mu/m CMOS transconductance-capacitor filter with enhanced linearity

Compact sub-hertz OTA-C filter design with MOS interface-trap charge pump

Linearized OTAs for high-frequency continuous-time filters: a comparative study

Design of RF integrated inductors by geometric scaling

Technology migration effects on signal integrity of single on-chip interconnect

Compact low-pass filter using a slow-wave structure

Design of transimpedance and limiting amplifiers for 10 Gb/s optical communication systems

A 5-Gbit/s CMOS optical receiver frontend

Development of an FPGA for multitechnology applications

Fabrication of cantilevered near-field probe arrays using MEMS technology

A new efficient dynamic-iterative technique for turbo decoders

Systolic equalizer structures

New pi-model of bipolar transistor noise for circuit analysis and simulation and technique to reduce phase noise in bipolar oscillators

Comparison of initial cell search algorithms for W-CDMA systems using cyclic and comma free codes

FPGA system-on-chip soft IP design: a reconfigurable DSP

Comparison of various numerically controlled oscillators

Rapidly reconfigurable coarse-grained FPGA architecture for digital filtering applications

Hardware efficient Octaphase-shift keying detector

Link adaptation and channel prediction in wireless OFDM systems

Channel equalization using adaptive subband filters

Series-cascade nonlinear adaptive filters

Symbol detection based on subspace method for diversity system

The circuit designs of an SRAM based look-up table for high performance FPGA architecture

A fast diagnosis method for interconnect fault in FPGA

Gigahertz FPGAs with new architectural ideas

Predicting the performance of FPGA routing algorithms

An efficient algorithm for frame-based signal processing

Low SNR BPSK signal chip rate estimation using a wavelet based spectral correlation algorithm

Design of mixed-domain filters for detection of arbitrary trajectory signals by using extended complex Kalman filters

Identification of two dimensional harmonics via 1-D polynomial root finding

Image watermarking using wavelets

A new video watermarking protocol

Digital image watermarking using singular value decomposition

An efficient pyramid for motion estimation

Traffic engineering optimal routing for LSP setup in MPLS

Handover control and analysis of WMPLS networks

MPLS-over-GRE based VPN architecture: a performance comparison

Analysis of GMPLS architectures, topologies and algorithms

Nonlinear analysis of EEG signals

Detection of defects in textures with alignment error for real-time line-scan web inspection systems

Discrete-space systems and Volterra series representations

Texture classification using discriminant wavelet packet subbands

A multistrategy signal pattern classifier

Timing jitter in a 1.35-GHz single-ended ring oscillator

Face recognition by means of template matching in frequency domain-a hardware based approach

A nonlinear method of frequency estimation in noise

Towards robustness in speaker verification: enhancement and adaptation

A study on the improvement of speaker recognition system by voiced detection

A robust algorithm for detecting speech segments using an entropic contrast

A text-independent speaker identification system using PARCOR and AR model

Performance of Internet and CDMA cellular data for voice over IP

Speaker identification employing waveform based speech CODEC

On the use of wavelet and Fourier transforms for speaker verification

Location of craniofacial landmarks on X-ray images by employing fuzzy neural network

Computer-aided approximation of circularly symmetric two-dimensional filters obtained by starting from separable 1-D transfer functions

Low-distortion continuous-time integrated filters for low frequency applications

Wide-tuning, low-voltage 1GHz bandpass filter based on f/sub T/-integration

CMOS circuits for thermal asperity detection and recovery in disk-drive read channels

A 0.8V CMOS filter based on a novel low voltage operational transresistance amplifier

A high gain 18 GHz single transistor frequency doubler

Fully differential, high-speed current-mode controlled dividers designed using modular approach

A very low power CMOS, 1.5 V, 2.5 GHz prescaler

Transient analysis of injection-locked frequency dividers

A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner

A CMOS phase/frequency detector with a high-speed low-power D-type master-slave flip-flop

Jitter analysis of a PLL-based CDR with a bang-bang phase detector

A novel design for deadzone-less fast charge pump with low harmonic content at the output

System analysis of a multi-standard direct conversion wireless receiver

Implementation of adaptive modulation on the Sunrise software radio

Game theoretic analysis of a network of cognitive radios

A programmable baseband processor design for software defined radios

Modeling and verification of a pipelined CPU

Access time and energy tradeoffs for caches in high frequency microprocessors

Design of 0.18 /spl mu/m CMOS test chip for package models and I/O characteristics verification

Computing the noise figure of most circuits by applying symbolic analysis

A high data transfer rate frequency shift keying demodulator chip for the wireless biomedical implants

Architectures and implementations of low-density parity check decoding algorithms

Beam-forming for MC-CDMA systems

High rate coded OFDM with channel equalization

Tapered transmission gate chains for improved carry propagation [arithmetic logic circuits]

Implementation of unidirectional CORDIC algorithm using precomputed rotation bits

High-speed hybrid threshold-Boolean logic counters and compressors

Low-voltage power-efficient adder design

A robust algorithm for identifying different types of engine misfires

A novel approach for single microphone active noise cancellation

A data-derived quadratic independence measure for adaptive blind source recovery in practical applications

A double binary-tree FIR-filter form and the corresponding low-sensitivity IIR bandpass/bandstop structure

Tunable bandpass passive digital filter design

One structure for efficient narrow-band bandpass FIR filters

ARMA lattice digital filter design

Network vulnerability analysis

Signaling system 7 (SS7) network security

Invisible Trojan: an architecture, implementation and detection method

Quantizing the throughput reduction of IPSec with mobile IP

A novel architecture for integrated CMOS wideband PLL-based frequency synthesizer

A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

Experimental performance of a coherent communication system based on hyperchaos synchronization

Configurable architecture for smart pixel research

Data rate enhancement of VDSL via termination impedance matching

Power/bit optimization of /spl Delta/-/spl Sigma/ ADCs using multi-bit quantizers

General-purpose fast-switching PLL IC for frequency synthesis

A 5 GHz, 1.5 V and very low-power CMOS frequency synthesizer for wireless communications

A completely integrated, low noise, low power CMOS frequency synthesizer for GSM communications

A ROM based fractional-N frequency synthesizer for wireless communications

Low voltage low power CMOS inductorless RF bandpass filter with high image rejection capability

Low voltage high Q VHF CMOS transistor-only active inductor

Technological limitations of monolithic high-frequency oscillators in MOS and bipolar processes

Characterizing metastability and jitter in CMOS latch/flip-flop used as a digital mixer

Design of a 1 V low power CMOS bandgap reference based on resistive subdivision

Low-voltage, supply independent CMOS bias circuit

A programmable monolithic temperature logging device

Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications

Interarrival jitter analysis of packet switched networks deploying differentiated services

An efficient digital down conversion method for multiple wideband signals

Mismatch effect on noise figure for WLAN receiver

Performance comparison of frequency domain processing and time domain processing in ultra wideband links

Application of layered space-time processing to ultrawideband communication

Issues in the performance and covertness of UWB communications systems

UWB channel impulse response characterization using deconvolution techniques

HDL synthesis and simulation of eight bit DSP based micro-controller for image processing applications

A 1.8-V frequency synthesizer for WCDMA in 0.18-/spl mu/m CMOS process

An investigation of timing jitter in bipolar ECL ring oscillators

Signal perception and processing with bioinspired sub-micro-systems

Convergence of iterative decoding for fixed-point implementations

Digital chaotic DS-CDMA communication system

An analog turbo decoder for an (8,4) product code

Time delay influence on the performance of adaptive turbo coded modulation

High-speed complex number multiplier and inner-product processor

Adiabatic 4-bit adders: comparison of performance and robustness against technology parameter variations

Graph-based optimization for a CSD-enhanced RNS multiplier

A novel approach to multiple constant multiplication using minimum spanning trees

Cascaded structures for blind source recovery

Recursive quadratically constrained least squares bias-free IIR system identification via variable loading

Steady state analysis of the p-power algorithm for constrained adaptive IIR notch filter

A unified framework for multichannel fast QRD-LS adaptive filters based on backward prediction errors

Fuzzy filters for image filtering

Plane wave filtering using a novel 3D cone-stop filter bank

Analytical design of frequency scaled asteroidal 2-D FIR filters

Realization of 2-D variable IIR digital filter structures with a small amount of calculations for coefficient update

WAID: wavelet analysis intrusion detection

Counter mode encryption for FNBDT/MELP

Simultaneous identity verification and membership proof

Volume 2 - 2002

Volume 1 - 2002

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)

1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg

Proceedings of the 39th Midwest Symposium on Circuits and Systems

38th Midwest Symposium on Circuits and Systems. Proceedings

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems

Proceedings of 36th Midwest Symposium on Circuits and Systems

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems

[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems

Proceedings of the 33rd Midwest Symposium on Circuits and Systems

Proceedings of the 32nd Midwest Symposium on Circuits and Systems,

Counter mode encryption for FNBDT/MELP

Content Provider	IEEE Xplore Digital Library
Author	Sleezer, R. Daniel, E. Raymond, J. Brewer, J. Teague, K.
Copyright Year	2002
Description	Author affiliation: Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA (Sleezer, R.; Daniel, E.; Raymond, J.; Brewer, J.; Teague, K.)
Abstract	Counter mode encryption is the proposed method for encrypting Mixed Excitation Linear Predictor (MELP) data for the Future NarrowBand Digital Terminal (FNBDT). Counter mode encryption employs an indefinite keypad generated by an encrypting function applied to a counter. The clear (unencrypted) data is exclusive-or-ed with the next available key in the pad. When encrypted data is received, the clear data may be retrieved by exclusive-or-ing the encrypted data with the same key used for encryption. The benefits and drawbacks of implementing counter mode encryption for real time MELP audio applications are presented.
Sponsorship	IEEE Circuits & Syst. Soc. School of Electr. & Comput. Eng. at Oklahoma State Univ
File Size	250295
File Format	PDF
ISBN	0780375238
DOI	10.1109/MWSCAS.2002.1187134
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Counting circuits Cryptography Protocols Codecs Narrowband Bandwidth NIST Speech Data engineering Information retrieval
Content Type	Text
Resource Type	Article

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