NDLI: Characterizing metastability and jitter in CMOS latch/flip-flop used as a digital mixer

Content Provider	IEEE Xplore Digital Library
Author	Shankar, I. Morris, S.A. Hutchens, C.G.
Copyright Year	2002
Description	Author affiliation: Sch. of Electr. & Comput. Sci. Eng., Oklahoma State Univ., Stillwater, OK, USA (Shankar, I.; Morris, S.A.; Hutchens, C.G.)
Abstract	A novel low power silicon-on-insulator (SOI) CMOS digital mixer circuit that is small, fully integrable and easily implemented is presented. This circuit is for use in a microbalance counter circuit (MBC) that operates at temperatures up to 180 degrees Celsius for petroleum industry well logging applications and has a measurement acquisition time of 2.4 seconds and a frequency resolution of 59 nHz when measuring 7 MHz signals. The digital mixer circuit eliminates the need for an analog mixer and bulky, temperature sensitive low pass filter components. This paper focuses on modeling and analysis of the metastable behavior and measurement inaccuracy caused by input phase jitter of the digital mixer. There is a risk of miscount due to jitter in the input signals. This paper explains how to model this risk and generate design parameters given the user's criteria for maximum risk of count errors.
Sponsorship	IEEE Circuits & Syst. Soc. School of Electr. & Comput. Eng. at Oklahoma State Univ
File Size	240937
File Format	PDF
ISBN	0780375238
DOI	10.1109/MWSCAS.2002.1187098
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Metastasis Jitter Flip-flops Temperature sensors Frequency measurement Time measurement Latches Silicon on insulator technology CMOS digital integrated circuits Counting circuits
Content Type	Text
Resource Type	Article

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