NDLI: HDL synthesis and simulation of eight bit DSP based micro-controller for image processing applications

Content Provider	IEEE Xplore Digital Library
Author	Rangarajan, P. Kutraleeshwaran, V. Vaasanthy, K. Perinbam, R.P.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Sri Venkateswara Coll. of Eng., Sriperumbudur, India (Rangarajan, P.)
Abstract	This paper deals with VLSI design and simulation of fast eight bit DSP based RISC micro controller for real time image processing applications. By exploiting inherent concurrency of two dimension recursive filters, Folded systolic architecture is designed and combined with HAVARD architecture. Due to pipelined features each instruction takes one clock period for execution. Apart from ALU, program memory (PRAM), data memory (CROM), four register banks, two stacks are incorporated in design. Control signals for folded architecture is generated in the HAVARD architecture of RISC processor. The folded architecture has seven column processors which are capable of handling forty-nine pixels in forty-nine clock periods. Each column processor has fixed point adder multiplier, latch and enable pin. The core has been designed using Verilog as HDL with SPARTAN SQSVQ100 as target FPGA device. Waveform of functional simulation of core confirms the micro-controller's capability of having throughput rate of ONE PIXEL PER CLOCK PERIOD.
Sponsorship	IEEE Circuits & Syst. Soc. School of Electr. & Comput. Eng. at Oklahoma State Univ
File Size	199524
File Format	PDF
ISBN	0780375238
DOI	10.1109/MWSCAS.2002.1187113
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Digital signal processing Image processing Clocks Reduced instruction set computing Very large scale integration Concurrent computing Filters Phase change random access memory Registers
Content Type	Text
Resource Type	Article

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