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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Arzt, U. Teich, J. Thiele, L. |
| Copyright Year | 1992 |
| Description | Author affiliation: Inst. of Microelectron., Saarland Univ., Saarbrucken, Germany (Arzt, U.; Teich, J.; Thiele, L.) |
| Abstract | Describes the concepts of a compiler for mapping programs onto massively parallel architectures, e.g. VLSI signal processing arrays, and general-purpose-type massively parallel architectures, e.g. digital signal processors. The input to the system is a single-assignment code. Using a transformative approach, the initial program is refined using provably correct program transformations in order to solve typical mapping problems. These are the localization of global data dependencies, the scheduling of computations in time and space, the generation of control, and the matching of resource constraints. After application of the architecture-independent transformation tools, a back end consisting of architecture-dependent generators creates output code from the transformed program. Thus, architecture-independent design of parallel programs is possible. The main concepts of the COMPAR design system are described. The software instances of the implementation are modeled, and the class of input programs is formally introduced. The design flow is explained by introducing the required program transformations. The main advantages of the system in comparison to similar design systems are outlined.< |
| Starting Page | 681 |
| Ending Page | 684 |
| File Size | 443661 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780305930 |
| DOI | 10.1109/ISCAS.1992.230160 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-05-10 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parallel architectures Signal processing algorithms Program processors Very large scale integration Aerospace electronics Computer architecture Algorithm design and analysis Parallel processing Array signal processing Pipeline processing |
| Content Type | Text |
| Resource Type | Article |
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