NDLI: A speed enhancing architecture for a floating point signal processor

Content Provider	IEEE Xplore Digital Library
Author	Spahlinger, G.
Copyright Year	1988
Description	Author affiliation: Inst. fuer Netzwerk-under Systemtheorie, Stuttgart Univ., West Germany (Spahlinger, G.)
Abstract	In contrast to fixed-point arithmetic, floating-point arithmetic requires more steps for a given operation, which normally slows down the execution speed of a floating-point processor. A special hardware architecture for minimizing this problem is proposed. The processor is a four-address machine with Harvard architecture. A two-level pipelining is introduced., i.e. fetching of operands and storing of the result are done in parallel with arithmetic calculations. This pipelining is invisible for the programmer, because a special register allows the access to the result of the last operation. The fundamental arithmetic operation is D=A+B*C.Addressing of operands is either direct or indexed with base offset and auto-modification. All of these addressing modes can be used independently for all of the four addresses in one instruction.<>
Starting Page	2039
Ending Page	2042
File Size	158530
Page Count	4
File Format	PDF
DOI	10.1109/ISCAS.1988.15342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-06-07
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing Registers Pipeline processing Fixed-point arithmetic Floating-point arithmetic Hardware Programming profession Multiplexing Random access memory
Content Type	Text
Resource Type	Article

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