NDLI: A new floorplanning method with global routing based on functional partitioning

Content Provider	IEEE Xplore Digital Library
Author	Ohmura, M. Izumoto, H. Fukii, T. Kikuno, T. Toshida, N.
Copyright Year	1988
Description	Author affiliation: Fac. of Eng., Hiroshima Univ., Japan (Ohmura, M.; Izumoto, H.; Fukii, T.)
Abstract	The authors propose a floorplanning method combined with global routing for VLSI layout design. In this method, issues of types of modules, critical nets, and functional relations between modules are explicitly taken into account at both the floorplanning and the global routing stages. Thus, it is expected that the proposed method obtains the chip floorplan such that (1) the estimated chip size satisfies a given aspect ratio, (2) the estimated chip area is minimum, (3) that routing area for each critical net is reserved in the chip, and (4) each switchbox is minimally congested. It is expected that the proposed method will yield a chip floorplan with the following characteristics; the estimated chip size satisfies a given aspect ratio and is minimal; the routing area for each critical net is reserved in the chip; and each switchbox is minimally congested.<>
Starting Page	1697
Ending Page	1700
File Size	200897
Page Count	4
File Format	PDF
DOI	10.1109/ISCAS.1988.15261
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-06-07
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Logic circuits Design engineering Integrated circuit layout Very large scale integration Shape
Content Type	Text
Resource Type	Article

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