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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Takach, A.R. Jha, N.K. |
| Copyright Year | 1990 |
| Description | Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Takach, A.R.; Jha, N.K.) |
| Abstract | Clocked differential cascode voltage switch (DCVS) circuits are dynamic CMOS circuits which have the advantage of being protected against test-set invalidation due to circuit delays. A C-testable DCVS design of a carry-save parallel multiplier is presented. This design is C-testable with only six test vectors which detect all detectable stuck-at, stuck-on, and stuck-open faults in the circuit. The hardware needed for an n*n multiplier consists of n(n-1) full-adders, a summand generator consisting of n/sup 2/ 2-input AND gates, as well as (at most) four extra 2-input AND gates to enhance the controllability of the circuit. An additional controllable input t is required. The design of the multiplier is discussed. The set of vectors to test the individual building blocks of the multiplier is presented. The input assignments to the DCVS multiplier, which result in the application of the appropriate tests to each module, are discussed, and the validity of the test set for detecting the detectable single stuck-at, stuck-open, and stuck-on faults is proved.< |
| Starting Page | 2732 |
| Ending Page | 2735 |
| File Size | 424629 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ISCAS.1990.112574 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-05-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Fault detection Switches Electrical fault detection Circuit faults Clocks Voltage Switching circuits Protection Delay |
| Content Type | Text |
| Resource Type | Article |
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