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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Diamantaras, K.I. Zimmermann, K.H. Kung, S.Y. |
| Copyright Year | 1990 |
| Description | Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Diamantaras, K.I.; Zimmermann, K.H.; Kung, S.Y.) |
| Abstract | A systolic architecture for two basic mathematical morphology operations is presented. Mathematical morphology has been proven to be a very useful tool for applications such as image restoration, image skeletonization, pattern recognition, machine vision, etc. The advantages of the design stem from the fact that it has a pipeline period alpha =1, requires simple communications, and exploits the simplicity of the morphological operations to make it possible to implement them in a linear target machine without using multiprojection, although the starting algorithm is a generalized two-dimensional convolution. The optimal partitioning strategy for a constrained mapping when the number of PEs is fixed is given, achieving 100% processor utilization, and a systolic chip design which is capable of real-time video performance is proposed as the basic processing element.< |
| Starting Page | 1442 |
| Ending Page | 1445 |
| File Size | 410056 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ISCAS.1990.112403 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-05-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Morphology Image restoration Pattern recognition Machine vision Algorithm design and analysis Pipelines Morphological operations Partitioning algorithms Convolution Chip scale packaging |
| Content Type | Text |
| Resource Type | Article |
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