NDLI: A 0.6 V ultra low voltage operational amplifier

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Fast global motion estimation for sprite generation

A novel predictive global motion estimation for video coding

PPFPS - a paraboloid prediction based fractional pixel search strategy for H.26L

Low-band-shift (LBS) motion estimation with symmetric padding in wavelet domain

Link adaptation and receiver design for enhanced General Packet Radio Services wireless networks

Bandwidth utilization and signal strength-based handover initiation in mobile multimedia cellular networks

Local resource management of distributed sensor networks via static output feedback control

Performance evaluation of Secure Remote Password protocol

Network optimization problem in tie-set flow vector space and information network resource management

A novel sparse adaptive algorithm using wavelets

Design method for optimal step size matrix of the affine projection algorithm using semidefinite programming

Enhanced adaptive sparse algorithms using the Haar wavelet

New adaptive Kalman filters using filter bank

A transmultiplexer-based adaptive filtering structure using a new adaptation scheme

Clustering in globally coupled system of chaotic circuits

Generalized synchronization on linear manifold in coupled nonlinear systems

Chaotic system reconstruction from noisy time series measurements using improved least squares genetic programming

Mapping atoms to nonlinear Chua's circuits

CMOS circuit design and implementation of the discrete time chaotic chip

CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network

A superregenerative receiver for phase and frequency modulated carriers

A 5-GHz prescaler using improved phase switching

A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA)

On the global robust stability of delayed neural networks

Oscillatory hysteresis associative memory

Implementation oriented theory design issues on the DTCNN template generation

Enlarging neural class detection capacity in passive sonar systems

Nonsymmetric PDF approximation by artificial neurons: application to statistical characterization of reinforced composites

Binary image rotation using cellular neural networks

The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques

A 10-bit 100-MS/s 50 mW CMOS A/D converter

A method for the estimation of aperture uncertainty in A-D converters

Measurement verification of estimation method for time errors in a time-interleaved A/D converter system

A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-/spl mu/m CMOS

A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter

A current steering CMOS folding amplifier

Matching considerations in I/Q A/D converter pairs

Formulation of INL and DNL yield estimation in current-steering D/A converters

Locating stuck faults in analog circuits

A decomposition method for analog fault location

A fault tolerant incremental design methodology

Testability of path history memories with register-exchange architecture used in Viterbi-decoders

A combined approach to validate the design of embedded network devices

Modeling a resonant LC tank circuit embedded in a VCO

A CMOS phase-locked loop with an auto-calibrated VCO

Analysis of VCO jitter in chip-package co-design

Transient bit error rate analysis of data recovery systems using jitter models

Discrete-time phase-locked loop as a source of random sequences with different distributions

A resistorless low current reference circuit for implantable devices

1.5V CMOS current reference with extended temperature operating range

Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique

A low-noise bandgap reference voltage source with curvature correction

Image-adaptive watermarking based on warped discrete cosine transform

Analysis and improvement of correlation-based watermarking methods for digital images

Independent component analysis of digital image watermarking

FRM based FIR filter design - the WLS approach

Optimization of frequency-response-masking based FIR filters with reduced complexity

Efficient implementation for cosine-modulated filter banks using the frequency response masking approach

Frequency response masking FIR filters with short delay

A modified structure for the design of sharp FIR filters using frequency response masking technique

Transcription of polyphonic signals using fast filter bank

Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family

Power-delay trade-offs in SCL gates

CMOS bulk input technique

Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D/sup 3/L (D/sup 4/L) logic styles

A critical look at design guidelines for SOI logic gates

Handset detector architectures for DS-CDMA wireless systems

VLSI architecture of digital matched filter and prime interleaver for W-CDMA

A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels

FPGA-based radix-4 butterflies for HIPERLAN/2

A high-speed FFT processor for OFDM systems

Linearity enhancement of multibit /spl Delta//spl Sigma/ modulators using pseudo data-weighted averaging

A novel technique to estimate the statistical properties of /spl Sigma/-/spl Delta/ A/D converters for the investigation of DC stability

A new kind of low-power multibit third order continuous-time lowpass /spl Sigma//spl Delta/ modulator

BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulator

A 2.5-V /spl Sigma//spl Delta/ modulator in 0.25-/spl mu/m CMOS for ADSL

Design considerations and experimental evaluation of a syllabic companding audio frequency filter

Direct noise analysis of log-domain filters

High-frequency dynamic translinear and log-domain circuits in CMOS technology

A micropower log domain FGMOS filter

Synthesis of a translinear analog adaptive filter

A novel integration of on-sensor wavelet compression for a CMOS imager

A CMOS imager with real-time frame differencing and centroid computation

A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm

A matrix transform imager allowing high-fill factor

A processing element architecture for high-density focal plane analog programmable array processors

A property of Jacobian matrices and some of its consequences

On spectral factorization in two-dimensions

Minimax design of 2-D IIR digital filters using sequential semidefinite programming

On the geodesic paths approach to multichannel signal processing

Improved wave-digital approach to numerically integrating the PDES of fluid dynamics

Physical synthesis for ASIC datapath circuits

Asynchronous circuit synthesis via direct translation

Logic synthesis for PLA with 2-input logic elements

Polynomial expansions over GF(2) based on fastest transformation

Circuit design from minimized Haar wavelet series

Seamless switching of scalable video bitstreams for efficient streaming

A dynamic frame-skipping video combiner for multipoint video conferencing

Efficient error recovery techniques in a novel multimedia streaming framework with peer-paired collaboration

MPEG-4 video error detection by using data hiding techniques

A robust fine granularity scalability using trellis based predictive leak

Analysis of interleaved converters with WTA-based switching

Analysis and design of PWM regulators for large-signal stability

A method for predicting the ZVS condition for the class E amplifier

Magnetizing inrush current of a transformer and a new technique of its computation

Lossless/lossy image compression based on non-separable two-dimensional L-SSKF

Integer- and rational-coefficient M-band wavelet

A multistage filterbank-based channelizer and its multiplier-less realization

The unified discrete Fourier-Hartley transforms: theory and structure

Linear phase IIR filter bank design by LMI based H/sub /spl infin// optimization

A monolithic CMOS VCO for wireless LAN applications

Low complexity OFDM receiver using Log-FFT for coded OFDM system

Design of an efficient OFDM burst synchronization scheme

A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems

A mixed-mode IF GFSK demodulator for Bluetooth

Response of coupled chaotic circuits to sinusoidal input signal

Solving ability of Hopfield neural network with chaotic noise and burst noise for quadratic assignment problem

Chaotic optimization for quadratic assignment problems

Analysis of a type of digital chaotic cryptosystem

Data transmission with adjustable security exploiting chaos-based pseudorandom number generators

A prefiltering approach to frequency offset estimation in AWGN

Application of digital wide band mismatch calibration to an I/Q receiver

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Measurement time requirement for generalized cross-correlation based time-delay estimation

A modified identification algorithm for linear systems with noisy input-output data

Application of the SD to LCTI systems. 1

Application of the SD to LCTI systems. 2

On inconsistent initial conditions for linear time-invariant differential-algebraic equations

Derivation algorithm of transfer functions of 2-D continuous-discrete systems

Cut-off frequencies in wide-band systems

Generalized LC multiple resonance networks

New circuits for realization of the 1st and 2nd order all-pass LC filters with a better technological feasibility

Immitance data modelling via linear interpolation techniques

Computing the elements embedded into a positive feedback loop

An efficient biasing technique suitable for any kind of the four basic amplifiers designed at nullor level

A robust method for equalizer design based on the impulse response symmetry

Analysis and optimization of CMOS LNA noise performance with channel resistance

Revisiting the sifting integral: an interesting special case

An automatic tuning scheme for high frequency bandpass filters

Concept of frequency-transconductance tuning of bipolar voltage-controlled oscillators

Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 /spl mu/m CMOS technologies

A radix-2/sup n/ vector inner product

A unified radix-4 partial product generator for integers and binary polynomials

A polynomial-based division algorithm

Sub-word and reduced-width Booth multipliers for DSP applications

Noise-tolerant design and analysis for a low-voltage dynamic full adder cell

A procedure for the piecewise-linear approximation of the resistive part of a cellular nonlinear network

Practical notes on two Volterra filter identification direct methods

5th order multi-tone Volterra simulator with component-level output

Nonlinear prediction of brain electrical activity in epilepsy with a Volterra RLS algorithm

An analysis of the Internet traffic by the method of surrogate data

A low-voltage CMOS class-AB operational amplifier

Common-mode response shaping in rail-to-rail op-amp input stages

A 0.6 V ultra low voltage operational amplifier

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

A low-voltage MOS cascode bias circuit for all current levels

A novel semi-private watermarking technique

A blind audio watermarking algorithm with self-synchronization

A robust DWT-based video watermarking algorithm

A data hiding for audio using band division based on QMF bank

A robust public watermark for halftone images

Autocorrelation - a new differentiating domain for multiple access wireless communications

Space-time coding for doubly selective channels

Channel estimation for long-code WCDMA

On the impact of correlated fading for MIMO-systems

A simple cumulant based approach for multiuser channel identification

An area-efficient CMOS band-gap reference circuit for low supply voltages

CMOS voltage interface circuit for low power systems

Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme

A wide-range and fixed latency of one clock cycle delay-locked loop

An all-digital phase-locked loop for high-speed clock generation

A pipelined temporal difference imager

Pixel-and-column pipeline architecture for FFT-based image processor

Architecture for an aVLSI stereo vision system

An arbitration logic for CIF 30f/s bi-directional codec with graphic accelerator

A highly integrated CMOS image sensor architecture for low voltage applications with deep submicron process

Delta-sigma modulator topologies with high immunity to pattern noise

An efficient technique to eliminate quantisation noise folding in double-sampling /spl Sigma//spl Delta/ modulators

A structure of cascading multi-bit modulators without dynamic element matching or digital correction

An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer

Space-time vector delta-sigma modulation

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A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect

Design of highly linear tunable CMOS OTA

A highly linear low-voltage MOS transconductor

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values

Analogue VLSI for temporal frequency analysis of visual data

The multiple input linear weighted differential amplifier: a new versatile analog circuit building block

A virtual point array for parabolic voltage interpolation

A mixed signal enhanced WTA tracking system via 2-D dynamic element matching

Pure-capacitance-load source-follower comparators for low-power winner-take-all circuitry

Algorithmic aspects of uncertainty driven scheduling

The bi-weighted TSP problem for VLSI crosstalk minimization

The prime-graph and Q-sequence for coding the floorplan

Quality of service routing: heuristics and approximation schemes with a comparative evaluation

On three-dimensional layout of de Bruijn networks

Potential/charge balance model for a floating gate EEPROM cell

Inductance modeling for on-chip interconnects

A tick based methodology for rapid predictive circuit modeling

Passive closed-form expression of RLCG transmission lines

Floating-gate EEPROM cell model based on MOS model 9

A robust video object segmentation scheme with prestored background information

Automatic video segmentation using a novel background model

A novel framework for semi-automatic video object segmentation

DWT based hierarchical video segmentation

Dynamics of a phase-controlled series-parallel resonant converter

Design of generalized class E/sup 2/ DC/DC converter

Bi-directional integrated charge pumps

Area efficient CMOS integrated charge pumps

Development of a single-phase half-bridge neutral point clamped converter and its applications

Perceptual quantization using JNLD thresholds

Sound specific modelling and synthesis with a new postfiltering in low bit rate speech coding

A new spectrum estimation method of a speech waveform by eliminating high frequency pitch period

A high quality re-quantization/quantization method for MP3 and MPEG-4 AAC audio coding

Stochastic resonance in speech recognition: differentiating between /b/ and /v/

A new class of dual-mode asymmetric microwave rectangular filters

Novel quasi-elliptic microstrip filter configuration using hexagonal open-loop resonators

On a transmission-line Butterworth lowpass filter using radial stubs

Noise performance of CMOS transversal bandpass filters

Design of a spiral-mode microstrip antenna and matching circuitry for ultra-wide-band receivers

Optimal receiver for ergodic chaos shift keying

On the optimal labeling for pseudo-chaotic phase hopping

On auto-correlation values of M-phase spreading sequences of Markov chains

Folded sums of chaotic trajectories distribute uniformly

On the correlation of non-jittered and chaotically-jittered PWM signals carrying maximum information

Volume 2 - 2002

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Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

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A 0.6 V ultra low voltage operational amplifier

Content Provider	IEEE Xplore Digital Library
Author	Yonghui Tang Geiger, R.L.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Yonghui Tang; Geiger, R.L.)
Abstract	A technique for low-voltage CMOS analog circuit design is presented in this paper. In this technique, voltage sources are added in series with the gates of the MOS transistors to lower the effective threshold voltages of the transistors. With the lowered effective threshold voltage, it is possible to build a host of analog circuit that operates with a decreased supply voltage. A 0.6 V ultra-low voltage two-stage operational amplifier (op amp) was designed in a standard 3.3 V 0.35 /spl mu/m CMOS process to validate the technique. Compared to its counterpart operating with a 3.3 V power supply at a much higher power level, the low-voltage op amp maintained the same gain-bandwidth product and most other key performance parameters.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	324294
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1010298
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage Operational amplifiers Threshold voltage Power supplies Analog circuits MOSFETs CMOS process Bandwidth Energy consumption CMOS analog integrated circuits
Content Type	Text
Resource Type	Article

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