NDLI: A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect

Content Provider	IEEE Xplore Digital Library
Author	Harrison, R.R.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Utah Univ., Salt Lake City, UT, USA (Harrison, R.R.)
Abstract	We present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors using bipolar transistors employed multiple differential pairs with input offset voltages used to shift the individual transfer functions. These voltages were chosen to maximize the linear range of the summed differential pair currents. Equivalent offset voltages were generated by sizing emitter areas appropriately. Similar techniques may be applied to MOS circuits by scaling W/L ratios, but transistor size increases exponentially as we extend the linear range by adding more differential pairs. We introduce a method of adding equivalent offset voltages by biasing the back gate (i.e., body) of well devices appropriately. Test circuits built in a standard 0.5 /spl mu/m CMOS process and using few transistors exhibit improved linear range over standard single-differential-pair transconductors.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	324042
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1010327
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transconductors MOSFETs Bipolar transistors Transfer functions Threshold voltage Circuit testing Transconductance Linearization techniques Cities and towns CMOS process
Content Type	Text
Resource Type	Article

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