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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yonghua Cong Geiger, R.L. |
| Copyright Year | 2002 |
| Description | Author affiliation: Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA (Yonghua Cong) |
| Abstract | Current source mismatch is a major source of nonlinearity in current-steering digital-to-analog converters (DAC). In order to achieve a given linearity specification at a given yield level, it is essential that the designer determine the:: minimum required matching accuracy of the unit current sources. Monte-Carlo simulations are very time-consuming and provide the designer with little insight to choose proper DAC architectures and make tradeoff between design specifications. The limited mathematical formulations that have appeared in the literature are based on nonstandard linearity definitions or oversimplifying statistical assumptions. In this paper, simple formulas are obtained that accurately describe the relationship between nonlinearity, bits of resolution, minimum required matching accuracy, and yield, which make it possible to optimize the DAC structure and achieve high performance with less cost and power consumption. |
| Sponsorship | IEEE IEEE Circuits & Syst. Soc |
| File Size | 420240 |
| File Format | |
| ISBN | 0780374487 |
| DOI | 10.1109/ISCAS.2002.1010182 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Yield estimation Linearity Signal resolution Cost function Energy consumption Digital-analog conversion Signal processing Gaussian distribution Voltage Calibration |
| Content Type | Text |
| Resource Type | Article |
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