NDLI: A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels

Content Provider	IEEE Xplore Digital Library
Author	Kwan-wai Wong Chi-ying Tsui Cheng, R.S.-K. Wai-ho Mow
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China (Kwan-wai Wong; Chi-ying Tsui; Cheng, R.S.-K.; Wai-ho Mow)
Abstract	Lattice decoding algorithms have been proposed for implementing the maximum likelihood detector (MLD), which is the optimal receiver for multiple-input multiple-output (MIMO) channels. However the computational complexity of direct implementation of the lattice decoding algorithm is high and the throughput is variable. In this work, a K-best algorithm is proposed to implement the lattice decoding. It is computational inexpensive and has fixed throughput. It can be easily implemented in a pipelined fashion and has similar performance as the optimal lattice decoding algorithm if high value of K is used. In this paper, we describe a pipelined VLSI architecture for the implementation of the K-best algorithm. The architecture was designed and synthesized using a 0.35 /spl mu/m library. For a 4-transmit and 4-receive antennas system using 16-QAM, a decoding throughput of 10 Mbit/s can be achieved.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	395493
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1010213
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Lattices MIMO Maximum likelihood decoding Computer architecture Throughput Maximum likelihood detection Detectors Computational complexity Libraries
Content Type	Text
Resource Type	Article

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