NDLI: Demo: An improved FPGA implementation of CNN Gabor-type Filters

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Demo: An improved FPGA implementation of CNN Gabor-type Filters

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Demo: An improved FPGA implementation of CNN Gabor-type Filters

Content Provider	IEEE Xplore Digital Library
Author	Cesur, E. Yildiz, N. Tavsanoglu, V.
Copyright Year	2012
Description	Author affiliation: Electronics and Communications, Engineering Department, Yildiz Technical University, Istanbul, Turkey, 34349 (Cesur, E.; Yildiz, N.; Tavsanoglu, V.) In this paper, a new Cellular Neural Network (CNN) structure for implementing two dimensional Gabor-type filters is proposed over our previous design. The structure is coded in VHDL and realized on a state of the art Altera Stratix IV 230 FPGA. The prototype supports Full-HD 1080p resolution and 60 Hz frame rate. One dedicated processor is used for each Euler iteration, where time step is taken as the same as optimum step size, and 50 iterations are implemented. The input/output, control, RAM and communication blocks of the realization are taken from our second generation real time CNN emulator (RTCNNP-v2).
Starting Page	1
Ending Page	2
File Size	410255
Page Count	2
File Format	PDF
ISBN	9781467302876
ISSN	21650179
e-ISBN	9781467302890
DOI	10.1109/CNNA.2012.6331472
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-29
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Streaming media Gabor filters Educational institutions Electronic mail Cellular neural networks Real-time systems
Content Type	Text
Resource Type	Article

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