NDLI: CESAR: Emulating Cellular Networks on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Muller, J. Becker, R. Muller, J. Tetzlaff, R.
Copyright Year	2012
Description	Author affiliation: Institute of Fundamentals of Electrical Engineering, Faculty of Electrical and Computer Engineering, Technische Universität Dresden, 01062 Dresden, Germany (Muller, J.; Becker, R.; Muller, J.; Tetzlaff, R.)
Abstract	Complex dynamical systems establish offer entirely new possibilities to the development of groundbreaking data processing methods. In the domains of image and video processing, locally coupled cellular array computers, based on Cellular Nonlinear Networks (CNN), accelerate the computation of large amounts of data in real-time, due to their inherent concept of massive parallelism. Current VLSI implementations however, are accompanied by several distinct drawbacks. The computational accuracy of most currently available systems is limited to 8 bit, and the volatilely capacitively stored state values of analogue realisations often lead to errors when multiple tasks are processed sequentially. Moreover, the systems hardly allow to run a CNN program code to provide the full functionality of a CNN-UM. In this contribution, the novel CESAR architecture is proposed for the digital emulation of a time-discrete CNN-UM. The programmable array computer facilitates the powerful computation of consecutive CNN operations and the cost-efficient implementation of several application-specific configurations with variable network size and data representation. The presented architecture retains the inherent parallel paradigm of CNN, and assigns one processing element to each cell of the network. The cell outputs are coupled and stored locally, thus minimising data exchange with external structures and maximising the computation speed. The internal fixed-point multiplications are accelerated by using on-chip DSP resources provided by current FPGAs. By this means, a CNN-based embedded system with 128 cells, a 3 × 3 neighbourhood and 18 bit data representation was implemented on a Xilinx Virtex-5 FPGA.
Starting Page	1
Ending Page	5
File Size	341602
Page Count	5
File Format	PDF
ISBN	9781467302876
ISSN	21650179
e-ISBN	9781467302890
DOI	10.1109/CNNA.2012.6331409
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-29
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Field programmable gate arrays Registers Couplings Random access memory Arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in