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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hee Cheol Choi Jaejin Park Seung-Bin You Ho-Jin Park Geun-Soon Kang Jae-Whui Kim |
| Copyright Year | 1999 |
| Description | Author affiliation: Syst. LSI Div., Samsung ELectron. Co., Yongin, South Korea (Hee Cheol Choi) |
| Abstract | A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively. |
| Starting Page | 190 |
| Ending Page | 193 |
| File Size | 423476 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780357051 |
| DOI | 10.1109/APASIC.1999.824060 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-08-23 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitors Linearity CMOS technology Analog-digital conversion Clocks Switching converters Switches Energy consumption Calibration Voltage |
| Content Type | Text |
| Resource Type | Article |
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