NDLI: A semi-folded instruction format for VLIW architecture

Content Provider	IEEE Xplore Digital Library
Author	Won-Kee Hong Seung-Yup Lee Shin-Dug Kim
Copyright Year	1999
Description	Author affiliation: Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea (Won-Kee Hong)
Abstract	The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.
Starting Page	95
Ending Page	98
File Size	462833
Page Count	4
File Format	PDF
ISBN	0780357051
DOI	10.1109/APASIC.1999.824037
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-08-23
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Computer architecture Computer science Electronic mail Optimizing compilers Insertion loss Degradation Cache memory Tail Performance evaluation
Content Type	Text
Resource Type	Article

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