NDLI: A 1.5 V 10-bit 25 MSPS pipelined A/D converter

Content Provider	IEEE Xplore Digital Library
Author	Hee Cheol Choi Ho-Jin Park Sung-Sik Hwang Shin-Kyu Bae Jae-Whui Kim Chung, P.
Copyright Year	1999
Description	Author affiliation: Syst. LSI Div., Samsung Electron. Co., Yongin, South Korea (Hee Cheol Choi)
Abstract	A 1.5 V 10-bit 25 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and a current reference generator for low-voltage operation. It also employs a novel dual-mode voltage booster to achieve good low-voltage operation as well as cost reduction. The current reference generator adopts a newly proposed self charge-pumping architecture with ring oscillator that keeps a reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm/sup 2/ (1700 um/spl times/1300 um) and dissipates 45 mW at 25 MHz clock rate with 1.5 V single supply voltage in measurement result. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.44 LSB and /spl plusmn/0.82 LSB, respectively.
Starting Page	170
Ending Page	173
File Size	383028
Page Count	4
File Format	PDF
ISBN	0780357051
DOI	10.1109/APASIC.1999.824055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-08-23
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Voltage Analog-digital conversion Costs Charge pumps Ring oscillators Temperature Voltage-controlled oscillators Clocks Area measurement
Content Type	Text
Resource Type	Article

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