NDLI: A general DSP processor at the cost of 23K gates and 1/2 a man-year design time

Content Provider	IEEE Xplore Digital Library
Author	Tell, E. Olausson, M. Liu, D.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng., Linkoping Univ., Sweden (Tell, E.; Olausson, M.; Liu, D.)
Abstract	This paper describes the design and implementation of a 16-bit fixed point DSP processor. The processor is intended as a platform for hardware accelerators and allows additional computational units and assembler instructions to be added. The I/O facilities can also be customized to the needs of a specific application. Benchmarking has shown that the processor, without any hardware accelerators, has a performance comparable to single MAC commercial DSP processors. The architecture has been successfully synthesized in a 0.13 /spl mu/m process, resulting in a net-list of about 23000 gates, and a clock frequency of 195 MHz, making the performance/gate count ratio very competitive. It is also small enough to integrate 100 heterogeneous processors on a chip for example for communication infrastructure applications. The complete design time, including architecture and instruction set planning, assembler, debugger, instruction set simulator, RTL code and complete verification was about half a person-year.
Sponsorship	IEEE Signal Process, Soc
File Size	265501
File Format	PDF
ISBN	0780376633
ISSN	15206149
DOI	10.1109/ICASSP.2003.1202452
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-06
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Costs Registers Hardware Computer aided instruction Digital signal processing chips Process design Benchmark testing Assembly Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A low power DSP core for an embedded MP3 decoder

A dynamic programming approach to complex allocation in a DSP pipelined processor

The digital signal processor Derby

An efficient parallel instruction execution method for VLIW DSP

DSP processor/compiler co-design: a quantitative approach

Optimized parallel implementation of polynomial approximation math functions on a DSP processor

An Open Modular Test Concept for the DSP KISS-16V2

Design of the Host Port Interface for Communication Based on DSP TMS320VC5402

Design and Realization of the Two-Way Signal Acquisition Module Based on TMS320VC5402 DSP

A general DSP processor at the cost of 23K gates and 1/2 a man-year design time

Similar Documents

A low power DSP core for an embedded MP3 decoder

A dynamic programming approach to complex allocation in a DSP pipelined processor

The digital signal processor Derby

An efficient parallel instruction execution method for VLIW DSP

DSP processor/compiler co-design: a quantitative approach

Optimized parallel implementation of polynomial approximation math functions on a DSP processor

An Open Modular Test Concept for the DSP KISS-16V2

Design of the Host Port Interface for Communication Based on DSP TMS320VC5402

Design and Realization of the Two-Way Signal Acquisition Module Based on TMS320VC5402 DSP

A general DSP processor at the cost of 23K gates and 1/2 a man-year design time